(1) Field of the Invention
This invention relates to a memory type semiconductor device and in particular, to an improved process for forming very narrow, closely spaced, buried conductive lines for read only memory (ROM) devices.
(2) Description of the Prior Art
In the quest to achieve microminiaturization of integrated circuit devices, individual elements have been made very small and the elements have been closely packed. As ROM's are scaled down in dimensions, there is a continuous challenge to maintain a sufficiently high punch-through voltage between the buried bit lines. In conventional methods for fabricating buried bit lines (normally buried N+lines) for a ROM, the photolithography resolution capability limits the minimum buried bit line width and spacings.
In the conventional prior art process, an insulating layer 12 (typically oxide) is deposited on a monocrystalline silicon substrate 10 as shown in FIGS. 1 through 3. Subsequently, a photoresist layer 14 is deposited over layer 12. As shown FIG. 2, the photoresist is exposed and developed to form openings 16 that define the closely spaced, narrow bit lines. Using layer 14 as an implant mask, impurity ions are implanted into the substrate 10 through openings 16. The remainders of layers 12 and 14 are removed. The substrate is subjected to an oxidizing atmosphere to oxidize the implanted regions 18 of the silicon substrate 10. The resultant silicon oxide regions 20 cause the implanted ions to further penetrate the substrate forming bit lines 22 beneath the regions. In the prior art process, the photolithography resolution capability limits the minimum openings 26 and spacing widths 24 in the photoresist used to form the bit lines and spacings. The process steps to complete the ROM device that follow the bit line fabrication are well known.
U.S. Pat. No. 5,025,494 discloses a process for forming buried line conductors under a thick oxide region in a semiconductor substrate. The oxide and impurity regions are formed by initially depositing a silicon oxide layer and an overlaying layer of silicon nitride on the surface of the substrate. After openings have been made through the layer, using conventional photolithographic techniques, impurity ions are implanted through the openings. The exposed substrate regions are oxidized using the process described in U.S. Pat. No. 3,970,486 or a high pressure oxidation process for forming field oxide regions. The lightly doped source and drain regions are formed in the substrate by forming a floating gate and conductive gate over the channel regions. The spacer sidewall structure are formed on the sides of the gates and the ion implantations made through the openings. The minimum width of the oxide regions is limited by photolithography resolution capabilities.
U.S. Pat. No. 5,196,367 discloses a process for forming semiconductor devices having field oxide isolation with a channel stop. A multilayer oxidation masking structure of a silicon oxide layer, a polycrystalline silicon layer and a silicon nitride layer is formed. The multilayer oxidation mask is patterned by removing the silicon nitride layer and a portion of the polycrystalline silicon layer in the areas designated to have field oxide isolation grown therein. A sidewall insulator structure is formed on the exposed sidewalls of the patterned oxidation mask. Impurities are implanted into the area designated to have field oxide isolation to form the channel stops. The sidewall insulator structure is removed leaving the oxidation masking layer. The field oxide insulator structure is grown by subjecting the structure to oxidation whereby the channel stop is confined under the field oxide isolation and not encroaching the planned device regions.